1. Field of the Invention
The present invention relates to the formation of integrated circuits, and, more particularly, to the control of processes used in the formation of integrated circuits.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors, formed on a substrate. These elements are connected internally by means of electrically conductive lines to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit and also reducing signal propagation delays. Thus, an increase of the speed of operation of circuit elements is made possible. In modem integrated circuits, design rules of about 90 nm or less can be applied.
Field effect transistors are used as switching elements in integrated circuits. They allow control of a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length may at least partially compensate for the corresponding reduction of the channel conductivity. Reducing the channel length, however, entails a plurality of issues associated therewith. First, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability. Second, a reduction of the channel length entails a corresponding reduction of the dimension of the gate electrode in the length direction of the field effect transistor.
Gate electrodes of field effect transistors can be formed by means of photolithographic and etching processes which will be described in the following with reference to FIGS. 1a–1c. FIG. 1a shows a schematic cross-sectional view of a printer 100. The printer 100 comprises a light source 111. A condenser 105 collects light 107 emitted by the light source 111 and focuses it to an objective 106. The objective 106 is adapted to image a reticle 108 to a semiconductor structure 101 provided in the printer 100. The reticle 108 comprises opaque portions 109, 110. Portions of the reticle 108 other than the opaque portions 109, 110 are permeable for the light 107.
In modem printers, the light source 111 can comprise an excimer laser adapted to emit light in the ultraviolet range of the electromagnetic spectrum. For example, the light source can comprise an argon fluoride (ArF) laser configured to emit light having a wave-length of about 193 nm. Typically, an excimer laser emits pulses of light. These pulses have durations in a range from about 5–10 nanoseconds and contain about 10 mJ of energy. The short duration of the pulses entails a large peak power of up to several MW of the pulses.
The semiconductor structure 101 comprises a substrate 102 on which a material layer 103 covered with a photoresist layer 104 is formed. The photoresist layer 104 can comprise a positive photoresist.
A more detailed cross-sectional view of the semiconductor structure 101 is shown in FIG. 1b. The substrate 102 comprises a first transistor element 130 and a second transistor element 131 which are separated and electrically insulated from each other by shallow trench isolations 121, 122, 123. The first transistor element 130 comprises a first active region 124. Similarly, the second transistor element 131 comprises a second active region 125. The material layer 103 and the photoresist layer 104 are formed over a gate insulation layer 120. The semiconductor structure 101 can be formed by means of methods known to persons skilled in the art comprising deposition, oxidation, ion implantation, photolithography and etching.
The photoresist layer 104 is exposed. To this end, the light source 111 is operated to emit the light 107. Thus, the reticle 108 is illuminated with the light 107. The objective 106 images the reticle 108 to the photoresist layer 104. The opaque portions 109, 110 of the reticle are imaged to regions 104a, 104b of the photoresist layer 104. Therefore, the regions 104a, 104b are substantially not irradiated with the light 107, whereas other portions of the photoresist layer 104 are irradiated with the light 107. Due to the irradiation, the photoresist in portions of the photoresist layer 104 other than the regions 104a, 104b is chemically modified.
A schematic cross-sectional view of the semiconductor structure 101 in a further stage of the photolithographic process according to the state of the art is shown in FIG. 1c. After the exposure, the semiconductor structure 101 is removed from the printer 100 and the photoresist layer 104 is developed. In the development, the photoresist layer 104 is exposed to a developer. The developer can comprise a liquid adapted to dissolve those portions of the photoresist layer which were chemically modified due to the irradiation, whereas the regions 104a, 104b are substantially not affected by the developer. Therefore, the regions 104a, 104b remain on the semiconductor structure 101, whereas the rest of the photoresist layer 104 is removed.
After the development, the regions 104a, 104b have a critical dimension 1. The critical dimension 1 may be influenced by properties of the photoresist layer 104, for example contrast and sensitivity of the photoresist. Moreover, the critical dimension 1 may depend on peculiarities of the exposure, such as an amount of light received by the irradiated portions of the photoresist layer 104, which, in turn, may depend on a duration of the exposure, an intensity of the light 107 emitted by the light source 111 and an absorbance of the condenser 105 and the objective 106 for the light 107.
An anisotropic etching process is performed. To this end, the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the material of the material layer 103, leaving the photoresist in the regions 104a, 104b and the material of the gate insulation layer 120 substantially intact. In anisotropic etching, an etch rate of substantially horizontal portions of the surface of the material layer 103, measured in a direction perpendicular to the surface, is significantly greater than an etch rate of inclined portions of the surface of the material layer 103. Therefore, portions of the material layer 103 under the regions 104a, 104b are substantially not affected by the etchant, whereas the rest of the material layer 103 is etched. The anisotropic etching process is stopped as soon as the gate insulation layer 120 is exposed. The portions of the material layer 103 under the regions 104a, 104b form a first gate electrode 126 and a second gate electrode 127. A length of the gate electrodes 126, 127 substantially corresponds to the critical dimension 1 of the regions 104a, 104b. 
After the etching, the regions 104a, 104b of the photoresist layer 104 are removed, which can be done by means of a resist strip process known to persons skilled in the art. Thereafter, a sequence of ion implantation processes can be performed in order to introduce ions of at least one dopant material in portions of the active regions 124, 125 adjacent the gate electrodes 126, 127. Thus, source and drain regions of the transistor elements 130, 131 can be formed.
The gate electrodes 126, 127 absorb ions impinging thereon in the ion implantation processes and thus protect portions of the active regions 124, 125 from being irradiated with the ions. Consequently, substantially no dopants are introduced into portions of the active regions 124, 125 under the gate electrodes 126, 127. These portions form channel regions of the transistor elements 130, 131. A length of the channel regions depends on the length of the gate electrodes 126, 127, which, in turn, corresponds to the critical dimension 1 of the portions 104a, 104b of the photoresist layer 104. Hence, the channel length of the transistor elements 130, 131 depends on the critical dimension 1 of the regions 104a, 104b. 
Since the critical dimension 1 can be influenced by various peculiarities of the exposure, such peculiarities might also affect the length of the channel regions of the transistor elements 130, 131. The channel length of a transistor element, however, may have an influence on the properties of the transistor element, as detailed above.
In order to avoid undesirable fluctuations of the properties of the transistor elements 130, 131, methods of run-to-run control can be applied. A method of run-to-run control according to the state of the art will be described in the following.
A model of the performed process is provided. The model relates a process input X and a process output Y with each other. The process input X comprises a parameter of the process which can be controlled by varying the process. For example, in the photolithographic process described above, the process input X may comprise an amount of light provided by the light source 111 in the exposure of the photoresist layer 104, which may be controlled by varying the power of the light source 111 or the time of exposure.
The process output Y comprises a quantity which characterizes a result of the process which is accessible to measurements. In the photolithographic process described above, the process output Y can comprise the critical dimension 1 of the regions 104a, 104b of the photoresist layer 104 remaining on the semiconductor structure 101 after the development. The critical dimension 1 can be measured by means of methods well known to persons skilled in the art, such as optical microscopy, electron microscopy or laser scanning.
The model is based on a linear relationship between the process input X and the process output Y and comprises a sensitivity parameter γ and a bias parameterb as expressed by the following mathematical relationship:Y=γX+b   (1)
The sensitivity parameter γ describes a variation of the process output Y caused by a variation of the process input X. The bias parameter b characterizes a portion of the process output which is substantially independent of the process input X. The sensitivity parameter γ is determined in advance by means of methods known to persons skilled in the art and remains fixed. Variations of the process are taken into account by varying the bias parameter b.
A plurality of runs of the process is performed. In the nth run, a process input value X(n) is applied, wherein an index n enumerates the runs of the process. Thereafter, a process output value Y(n) of the nth run is measured. Then, a bias parameter value b(n+1) which is expected to occur in the next run is calculated by inserting the process input X(n) and the process output Y(n) into equation (1) and solving for the bias parameter b:b(n+1)=Y(n)−γX(n)  (2)
The bias parameter value b(n+1) and the sensitivity parameter γ are then used to calculate a process input X(n+1) which is applied in the next run by means of the following equation:
                              X          ⁡                      (                          n              +              1                        )                          =                              T            -                          b              ⁡                              (                                  n                  +                  1                                )                                              γ                                    (        3        )            
Here, T is a target value of the process output Y. If the method of run-to-run control is applied to the photolithographic process described above, the target value T can comprise a desired value of the critical dimension 1.
A problem of the method of run-to-run control of a photolithographic process described above is that a precision of the values of the process output Y obtained by means of the method can be insufficient for modern methods of manufacturing semiconductor structures.
In view of the above problem, there is a need for a method of run-to-run control allowing more precise control of the process output. Moreover, there is a need for a method allowing more precise control of a critical dimension of features formed in a semiconductor structure.